1. Technical Field
The present invention relates to a nonvolatile semiconductor memory device, such as a NAND nonvolatile semiconductor memory device, capable of being manufactured by a simplified process and having an increased storage capacity.
2. Description of Related Art
NAND nonvolatile semiconductor memory devices includes a series connected plural transistors as memory cells each including a charge storage layer in a gate insulating film and select gate transistors (generally, MOS transistors) respectively connected to the two ends of the series connection. As an example of the transistor used for the memory sell, there is used the following transistors: a memory cell transistor having a layered gate structure including a floating gate electrode layer; or a memory cell transistor having MONOS structure or SONOS structure, which includes an insulating film (ONO structure) as a gate insulating film having a silicon oxide film/silicon nitride film/silicon oxide film layered structure.
When the select gate transistor has the same layered structure as the memory cell transistor, electrons or holes may be stored in the charge storage layer of the select gate transistor due to, for example, voltage stress at the time of read state although it is not intended to perform write or erase operations on the select gate transistor as a target. In this case, when the select gate transistor is n-channel MOS transistor, the select gate transistor is not turned on because of increase of the threshold voltage or is not turned off because of decrease of the threshold voltage, which results in that the selectivity is impaired. For this reason, the select gate transistor needs to be formed by a different manufacturing process than the memory cell transistors.
In case where the memory cell transistor has the ONO structure, after a silicon oxide film, a silicon nitride film, and a silicon oxide film are formed on a silicon semiconductor substrate, or after a silicon oxide film and a silicon nitride film are formed on a silicon semiconductor substrate, the formed insulating films are removed in a region for forming a select gate transistor, a silicon oxide film is then formed at the region by oxidation, and a select gate transistor is finally formed as a usual MOS transistor.
In case where the memory cell transistor has the floating gate structure, it is desirable that the select gate transistor and the memory cell transistor have the same structure in a gate processing including lithography. Therefore, although the gate electrode of the lower layer is not separated for each select gate transistor, the select gate transistor also becomes a two-layer structure. However, it becomes a floating gate structure as it is and thus it is necessary to provide a contact portion of a two-layer gate including a floating gate electrode layer and a control gate electrode layer at a cell array end or in a cell array.
As described above, the presence of the select gate transistor complicates the manufacturing process. Furthermore, spaces for forming separated gate insulating films or regions for short-circuiting the two-layer gate electrodes are needed between the select gate transistors and the memory cell transistors, which result in increase in the memory cell size or the memory cell array area.
JP-A-5-326892 (see FIG. 4 of this document) discloses a NAND nonvolatile semiconductor memory device in which a diode, instead of the source-side select gate transistor, is connected in series to the memory cell transistors. Write operation is prohibited by charging-up of the channel region by utilizing the characteristics of the diode to turn off when a reverse voltage is applied. At the time of read operation, the diode is turned on by applying voltage to the source line side and voltage is applied to the gate electrodes of the memory cell transistors which are connected to the diode in series. A “1” or “0” state of the memory cell transistor of a target memory cell can be read out depending on whether it is on or off.
US 2004/0124466 A1 and A. J. Walker et al. (“3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications,” 2003 Symposium on VLSI Technology Digest of Technical Papers, June 2003) discloses an example in which memory cell transistors, which are thin-film transistors (TFTs) having an ONO structure charge storage dielectric layer are connected to each other in series to form a NAND string, are applied to a 3D flash memory. Likewise, US 2004/0155302 A1 discloses a 3D mask programmable ROM and its peripheral circuit configuration.
Although the storage capacity of memories has been increased by the miniaturization, investments are increasing as the degree of miniaturization increases. As a result, a tendency to produce an inexpensive, high-capacity layered memory using facilities which are low in running cost though the process is long is now increasing (see the document by A. J. Walker et al referred above).
M. Johnson et al. (“512-Mb PROM with a Three-Dimensional Array of Diode/Antifuse Memory Cells,” IEEE J. Solid-State Circuits, Vol. 38, No. 11, pp. 1,920-1,928, November 2003) discloses a 3D PROM including diode/antifuse memory cells having a stacked structure in which eight layers are stacked in the vertical direction. Furthermore, K-D. Sung et al. (“A 3.3-V, 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” 1995 IEEE International Solid-State Circuits Conference, pp. 128-129, Feb. 15-17, 1995) discloses an incremental step pulse programming (ISPP) NAND flash memory capable of reducing the page program current by self-boosting the program suppression voltage and capable of attaining high-speed read throughput by interleaved data paths.